This invention relates to an integrated circuit having a high-power DMOS transistor integrated with low-power small-signal-handling bipolar and CMOS transistors.
It is well known to integrate small-signal low-power transistors with a large-power-handling transistor. Only recently have lateral DMOS transistors and small-signal-handling bipolar transistors been integrated.
The load current in a lateral DMOS transistor flows "horizontally" in the channel and drift region to the drain contact, i.e. in a direction parallel to the major outer surface of the integrated circuit die and is capable of operational high drain to source voltages, e.g. over 500 volts. Lateral DMOS transistors are readily integrated since its structural parts are all located close to the surface of the die. Also, voltage breakdown occurs at the highest voltage gradient point in the lightly doped portion of the drain, typically an epitaxial layer portion of an integrated circuit, and since the voltage gradient is itself horizontal, the epitaxial layer thickness need not be abnormally thick, so that the difficulties of forming deep diffusions for isolation walls and plugs are greatly ameliorated.
It has been suggested that for integrating a lateral NPN transistor with a lateral DMOS transistor the base and D-well may be formed simultaneously, but compromising the performance of the lateral NPN transistor because the optimum P-dopant concentrations for the base and D-well are not the same.
However, such a lateral DMOS power transistor, when integrated with a vertical NPN transistor, is made by forming the NPN base in a separate step prior to forming the D-well of the DMOS transistor because the base width in the vertical NPN must be kept small (in the vertical direction) to maintain high gain whereas the corresponding vertical distance between the source and the bottom of the D-well in the lateral DMOS transistor must be substantially thicker to avoid voltage breakdown due to punch-through degrading the high voltage capability for which the lateral DMOS transistor is best suited.
The current-carrying capability of a lateral DMOS transistor is limited, especially by the relatively high resistance of the long epitaxial portion of the drain that is required to support the high drain voltage.
Vertical DMOS transistors are known to provide better current-carrying capability and at the same time can sustain moderately high voltages, e.g. 100 volts. Vertical DMOS transistors are more suitable for driving solenoid motors and other high current loads. However, the integration of a vertical DMOS transistor is more difficult. The epitaxial layer must be thick enough that breakdown due to punch-through in the epitaxial portion of the drain between the D-well and N+ buried layer must have a very low resistance connection to a contact region at the epitaxial outer surface via an extensive N+ plug. These are two rather incompatible requirements that imply compromises in die size and severe limitations respecting the possible sequences process steps.
It is an object of this invention to provide an improved method for making a vertical DMOS transistor of high current carrying capability integrated with small signal vertical NPN transistors.
It is a further object of this invention to provide such an integrated circuit made by a method that is efficient with respect to the number of steps required.
It is a further object of this invention to provide such an integrated vertical DMOS transistor that has self-aligned gate, channel and source regions.
It is a further object of this invention to provide such an integrated circuit additionally including small signal CMOS transistors.